The present invention relates to a semiconductor memory device, and more particularly to a technique for controlling a bulk bias voltage for a column decoder in a bank in which a large amount of off-leakage current occurs.
A dynamic random access memory (DRAM) device has an advantage of very large integration over other memory devices since it employs memory cells each of which is constructed with a transistor and a capacitor. Further, the DRAM device has been advanced in operational speed as various techniques have been proposed in conformity with recent high-speed requirements.
Accordingly, a DRAM device having the advanced driving capability at even a low voltage has been developed, and further, such DRAM device has been gradually spread to applications such as appliances and mobiles consuming a low power as well as a main memory of a computer.
It, however, becomes more and more difficult to implement a low standby current due to the high integration of the semiconductor memory device, wherein ensuring the low standby current means the minimization of off-leakage current for each device.
FIG. 1 is a table showing a value of off-leakage current per component calculated by summing widths of transistors presented in each of the components of a semiconductor memory device, e.g., a bank, a voltage generator and peripheral circuits.
The off-leakage currents occurring in the bank, the voltage generator and the peripheral circuits are 40.2 μA, 6.2 μA and 12.4 μA, respectively.
In conclusion, most of the total widths of transistors and thus off-leakage currents in the semiconductor memory device are substantially taken by transistors assigned to the bank. In particular, it is a column decoder that takes the largest width and the greatest amount of off-leakage current in the bank, and inter alia, the off-leakage currents occurring in a final driving unit and a pre-driving unit of the column decoder take up 42.8% of off-leakage currents occurring in the bank as can be seen from FIG. 2.
FIG. 2 shows a simulative result for an off-leakage current level per element obtained by producing the off-leakage current in each element of the bank. As can be seen from the simulative result, the off-leakage current produced by the column decoder takes up more than 50%.
FIG. 3 illustrates a detailed circuit diagram of a conventional column decoder 5 in a semiconductor memory device.
The conventional column decoder 5 includes a pre-driving unit 1 and a driving unit 2.
The pre-driving unit 1 has a PMOS transistor P1 and NMOS transistors N1 to N3 connected in series between a power supply voltage terminal VDD and a ground voltage terminal VSS. The PMOS transistor P1 and the NMOS transistor N1 have a common gate and are provided with a control signal BYP through the common gate, the control signal BYP being a pulse signal containing bank information. Further, they have a common drain which acts as an output node of the pre-driving unit 1 to output a state output signal to the driving unit 2. The NMOS transistors N2 and N3 receives code signals YCOD1 and YCOD2 through their gates, respectively, wherein each of the code signals YCOD1 and YCOD2 has a code containing column address information for a corresponding cell of a multiplicity of cells in a cell matrix 3 in the semiconductor memory device.
The driving unit 2 has a PMOS transistor P2 and an NMOS transistor N4 connected in series between the power supply voltage terminal VDD and the ground voltage terminal VSS. The PMOS transistor P2 and the NMOS transistor N4 have a common gate acting as an input node of the driving unit 2 and a common drain acting as an output node of the driving unit 2.
The input node of the driving unit 2 is connected with the output node of the pre-driving unit 1 to receive the state output signal from the pre-driving unit 1. If a certain condition is met as described later, the driving unit 2 generates a corresponding column selection signal, e.g., Yi0, to the cell matrix 3. The column selection signal Yi0 indicates an address of the corresponding cell, commonly designated by the two-code signals YCOD1 and YCOD2, in the cell matrix 3.
The PMOS transistors P1 and P2 receive a power supply voltage VDD through their bulk and the NMOS transistors N1 to N4 receive a ground voltage VSS through their bulk.
For the purpose of forming one bank, a plurality of above-assembled column decoders are required and thus a plurality of column selection signals, e.g., Yi0 to Yin, are outputted to the cell matrix 3, n being a positive integer.
The pre-driving unit 1 receives the code signals YCOD1 and YCOD2 required for the column selection and selects one of the column decoders into which the code signals YCOD1 and YCOD2 having an enabled state, e.g., a logic high level, are inputted, thereby enabling a corresponding column selection signal, e.g., Yi0.
More specifically, when a column access operation for the column selection is not performed, the control signal BYP has a disabled state, e.g., a logic low level, thereby setting the column selection signal Y1 to a disabled state, e.g., a logic low level. On the other hand, when the column access operation for the column selection is performed, the control signal BYP is enabled to a logic high level. When the control signal BYP is enabled, if the code signals corresponding to a certain one of the column decoders have the enabled state, the pre-driving unit 1 of the certain column decoder is enabled, such that the PMOS transistor P2 of the driving unit 2 is turned on and thus the column selection signal Yi0 is enabled and outputted to the cell matrix 3.
There is a need to reduce off-leakage currents in the semiconductor memory device by controlling the column decoder in which a substantially large amount of the off-leakage current occurs.